The present invention relates to an information processor having an instruction buffer, and particularly to an information processor which is designed to increase the whole processing speed by improving the hit rate of the instruction buffer.
A variety of improvements have been made in the execution control to increase the processing speed of the information processors as described in "Computer Architecture and Parallel Processing" by Kai Hwang et al, 1984 Mcgraw-Hill pp. 187 to 193. In the conventional instruction buffer, it is taught that several instructions among the instruction words in the main memory are stored in advance in a memory of a small capacity for high speed accessing, thereby to reduce the time for reading the instruction words and, hence, to increase the processing speed. In particular, when the loop of instructions capable of totally residing in the instruction buffer is executed repetitively, the especially stored instruction words are not re-executed at the later executions later, thereby making it possible to efficiently increase the speed of processing. The above-mentioned case is referred to as the capture of a loop of instructions.
There is an algorithm (called replacement algorithm) for determining that location in the instruction buffer that stores the next instruction to be executed when it is not in the instruction buffer. In general, such an algorithm employs a method (First In First Out, FIFO) for storing the next instruction at the location of the old instruction in the instruction buffer, or a method (Least Recently Used, LRU) for storing the next instruction at the location of the instruction that was not referred to for the longest period of time.
The probability (hit rate) that the instruction to be executed next is stored in the instruction buffer increases with the increase in the capacity of the instruction buffer, whereby the probability of capture of the loop of instructions increases, too. In the case of a loop of instructions greater than the capacity of the instruction buffer, however, the instructions are expelled from the instruction buffer before they can be executed despite the same instructions being repetitively executed many times. Therefore, the instructions are read out from the main memory before they can be re-executed, and the efficiency decreases significantly. This phenomenon also develops even when the replacement algorithm is FIFO or LRU.